1. Field of the Invention
The present invention relates in general to integrated circuit (IC) wafer testers and in particular to a system for calibrating signal timing of IC wafer tester channels to compensate for variation in signal paths between the tester and test probe points on a calibration substrate.
2. Description of Related Art
Integrated circuits (ICs) are fabricated in the form of die on a semiconductor wafer but are thereafter separated and packaged. To avoid the cost of packaging defective ICs an IC tester can test ICs while they are still in wafer form. An IC tester tests an IC by sending a sequence of test signals to its input terminals and monitoring the output signals produced by the IC to determine whether they behave as expected. A typical integrated circuit tester includes a xe2x80x9ctest headxe2x80x9d containing circuit boards implementing a set of tester channels, each capable of sending a test signal to the IC or of sampling an IC output signal to determine its state. An interconnect system links each tester channel to a separate I/O terminal (usually a bond pad) of a die on the wafer under test. A typical interconnect system includes a xe2x80x9cprobe cardxe2x80x9d having an upper surface including contact points for receiving tips of pogo pins extending downward from the test head for conveying signals between the channels in the test head and the probe card. A set of probes on an under surface of the probe card are arranged to contact the IC""s bond pads. The probe card also includes vias and other conductors for interconnecting the probes and the pogo pin contacts. Since the product of the number of I/O terminals on a die and the number of die on a wafer usually exceeds the number of available channels on a tester, the tester usually tests part of the wafer per probe touchdown, sometimes only one die. A xe2x80x9cprober-stepperxe2x80x9d that holds the wafer while being tested, appropriately positions the die to be tested under the probes and brings the wafer into contact with the probe tips during testing. After each test is completed the prober-stepper repositions (steps) the wafer so that the probes access a next set of die to be tested.
To properly test an IC, a tester must coordinate the timing of the channels"" test activities. When a first tester channel changes the state of a test signal at some IC input terminal, we might expect a second tester channel to observe a particular state change in an IC output signal appearing at another IC output terminal a specific time thereafter. We consider an IC to be defective when an appropriate IC output signal state change does not occur with the correct delay following an IC input signal state change. Thus the tester must closely coordinate the time at which the first tester channel changes the input signal state with the time at which the second tester channel samples the IC output signal to determine its state.
An IC tester synchronizes all test events to a periodic master clock signal supplied to all of its channels. The channels time their activities relative to the timing of edges of that master clock signal. However merely supplying the same master clock signal to all channels is not sufficient to ensure that they will precisely coordinate their event timing. One reason for this is that since the channels reside in separate locations within the test head, differences in the lengths or electrical characteristics of the separate paths the clock signal path must travel to reach the channels causes the clock signal edges to arrive at the channels at different times.
Differences in timing can also arise from differences between channels. While all tester channels are of identical design, process variations in ICs and other components forming the channels cause some channels to process signals slightly faster than others. Also since the channels reside in separate locations within the test head, they may operate in differing temperature environments or may be subject to differing levels of stray capacitance or other environmental factors that influence the speed with which signals pass through internal circuits and conductors within each channel.
Variations in the lengths or impedance characteristics of signal paths through the interconnect system linking the tester channels to the wafer also cause timing variations between the channels.
To provide more precise timing coordination, it is necessary to calibrate the timing of each channel to reduce the timing variations caused by such factors. A typical tester channel includes a timing signal generator producing a set of timing signals of varying phase relative to the master clock signal. The timing signals control the timing of various test events such as the state changes in the test signal sent to the IC or the sampling of DUT output signals. Tester channels also include mechanisms for delaying test activities by an adjustable amount to compensate for timing differences between channels.
To make use of such timing calibration systems test engineers separately monitor the timing of signals produced at each channel""s test activities relative to a common timing reference and iteratively adjust each channel""s timing delay as necessary to synchronize the channels. For example test engineers commonly program all channels to produce a test signal pulse in response to each edge of corresponding timing signals, use an oscilloscope or other device to measure timing differences between edges of timing signals produced at the each channels"" I/O terminals, and adjust the timing calibration of all channels so that corresponding timing signal edges produced by all channels are concurrent. The monitoring of test signal edge timing at the channel I/O terminals rather than at the tips of the probes that contact the device under test does not account for differences in the signal paths provided by the interconnect system linking the channel I/O terminals to wafer bond pads. However test signal edges are monitored at the channel I/O ports, rather than at the probe tips because timing skew caused by interconnect system signal path differences can often be ignored. It is also much easier for an oscilloscope or other monitoring equipment to access the channel I/O terminals than to access the probe tips because the channel I/O terminals are much larger and more widely spaced than the probe tips.
However as the operating frequency of ICs has continued to increase, the resolution with which a tester must time test events has also increased to the point where even small variations in signal paths through the interconnect system can no longer be ignored. Therefore what is needed is a system for easily measuring timing differences between channels at the tips of the probes that contact the wafer under test.
The invention relates to a timing calibration system for a wafer level integrated circuit (IC) tester. The tester includes a set of probes for contacting pads on a surface of an IC and having a plurality of tester channels. Each channel generates a TEST signal at a tip of a corresponding probe in response to a periodic CLOCK signal with a delay adjusted by drive calibration data supplied as input to the tester channel. The TEST signal produced by each channel includes edges occurring in a timing pattern controlled by programming data provided as input to each tester channel.
In accordance with one aspect of the invention, to calibrate test signal timing of all channels, each channel is programmed to generate a test signal having the same repetitive edge timing pattern at the tester channel""s corresponding probe tip.
In accordance with another aspect of the invention, the test signal produced at each probe tip is then cross-correlated to a periodic reference signal having the same repetitive edge timing pattern.
In accordance with a further aspect of the invention, drive calibration data of each channel is then iteratively adjusted to determine a value which maximizes the cross-correlation between its output test signal and the reference signal. This ensures that all tester channels delay similar test signals by similar intervals.
In accordance with yet another aspect of the invention, each repetition of the test and reference signal edge pattern provides pseudo-randomly distributed time intervals between successive signal edges. This helps to maximize the accuracy of the timing calibration by ensuring that the test signals have a wide range of frequency components so the timing calibration process takes into account frequency-dependent delay characteristics of the signal paths conveying the test signals to the IC.
It is accordingly an object of the invention to provide a system for adjusting the test signal calibration delays of IC tester channels so that their test signal timing may be closely coordinated.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.